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Fault detecting experiments for sequential circuits

Fault detecting experiments for sequential circuits,10.1109/SWCT.1964.8,F. C. Hennine

Fault detecting experiments for sequential circuits   (Citations: 195)
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This paper describes the design of experimental procedures for determining whether or not a sequential switching circuit is operating in accordance with a given state-table description. These procedures are particularly easy to apply when the given state table is reduced, strongly-connected, and has a distinguishing sequence, and when the actual circuit has no more states than the given table. They can also be extended to cover more general cases, although the resulting experiments are more cumbersome.
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    • ...EST generation from a Finite State Machine (FSM) is a long-standing research problem, with numerous contributionsoverdecades.SincetheseminalworkofMoore[12] and Hennie [8], several methods have been proposed to generate a test suite with full fault detection capability, i.e., a test suite which provides full coverage of the set of all possible FSMs with a certain number of states that model implementations of a given specification FSM; such ...
    • ...If the FSM is completely specified and has a diagnostic sequence, a complete test suite with a single sequence can be generated, as in, e.g., [5], [9], [10], [8], [18]...
    • ...If the test suite possesses only a single maximal test, this can be accomplished by using a homing sequence, as in [8], [9], [18]...
    • ...In words, a confirmed set of input sequences contains transfer sequences for all states of M and any sequences converging (i.e., leading to a same state) in any FSM that has the same output responses to T and has as many states as M also converge in M. This key property is exploited by methods for constructing complete test suites, such as [1], [2], [4], [5], [9], [10], [8], [15], [17], [18], [20], in one way or another...

    Adenilso da Silva Simãoet al. Checking Completeness of Tests for Finite State Machines

    • ... we can produce input sequences to reach and distinguish states; these sequences will be used in the test generation algorithm given in Section 6. When testing from a deterministic FSM, it is normal to test a transition t by applying an input sequence that reaches the starting state of t, then the input from t and nally input sequences that distinguish between the ending state of t and all other states of the FSM (see, for example, [6, ...

    Robert M. Hieronset al. Testing from a stochastic timed system with a fault model

    • ... example, when testing from a nite state machine M with n states the fault domain might be the set of nite state machines that have the same input and output alphabets as M and at most m states for some predened m n. Fault domains can be used to reason about test eectiv eness and drive test data generation: we aim to produce test cases that distinguish between M and the elements of that do not conform to M (see, for example, [Chow 1978; Hennie ...
    • ...then produces a failure on at least one test case from X . There has been much interest in the automated generation of a checking experiment from an FSM (see, for example, [Chow 1978; Hennie 1964; Inan and Ural 1999; Luo et al. 1994; Luo et al. 1994; Petrenko et al. 1994; Petrenko et al. 1996; Petrenko and Yevtushenko 2005; Rezaki and Ural 1995; Ural et al. 1997; Yevtushenko et al. 1991])...
    • ...Previous work has shown how the existence of a fault domain can sometimes allow us to conclude that the SUT is correct on the basis of a set of observed traces (see, for example, [Hennie 1964])...

    Robert M. Hierons. Verdict functions in testing with a fault domain or test hypotheses

    • ...This test sequence is a checking sequence if it has the following property: if N ∈ Φ(M) then N passes the test sequence if and only if N is equivalent to M [10], [12]...
    • ...Earlier methods use some predefined strategies to reduce the length of transfer paths [12], [11]...
    • ...In the method proposed by Hennie [12], henceforth called...
    • ...Algorithm 1 checking sequence generation algorithm [12] 1: Input M and ADS θ of M. 2: Define a permutation s1,...,sn of the states of M. 3: for all 1 ≤ i ≤ n do 4: define a transfer sequence Ti such that Di/λ(si,Di)Ti labels a path with starting state si and terminating state si+1 ,w heresn+1 denotes s1 5: end for 6: Let CS = D1/λ(s1,D1)T1D2/λ(s2,D2)T2...Dn/λ(sn,Dn)...

    Robert M. Hieronset al. Checking Sequence Construction Using Adaptive and Preset Distinguishin...

    • ...The checking sequence determines whether N is a correct or faulty implementation of M [2, 3]...
    • ...paths as short as possible [3, 5] while constraints are enforced in the applied procedure...

    Guy-vincent Jourdanet al. Using a SAT solver to generate checking sequences

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