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Multi-valued Logic Addition and Multiplication in Galois Field

Multi-valued Logic Addition and Multiplication in Galois Field,10.1109/ACT.2009.190,V. K. S. Patel,K. S. Gurumurthy

Multi-valued Logic Addition and Multiplication in Galois Field   (Citations: 2)
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This paper presents addition and multiplication in Galois field using multi-valued logic. Multi-valued logic (MVL) has matured to the point where four-valued logic is now part of commercially available VLSI IC's. Modulo-4 addition and multiplication is also presented in this paper. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
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